****library: "leparts"
version: 6.07as
aids: 15
aidname: user
aidname: io
aidname: dbmirror
aidname: compaction
aidname: pla
aidname: routing
aidname: silicon-compiler
aidname: vhdl-compiler
aidname: compensation
aidname: logeffort
variables: 24
LE_drive_attr[04,00/0400]: "S"
LE_last_global_fanout_effort[05,00/0400]: 4.500000
LE_last_convergence_epsilon[05,00/0400]: 0.100000
LE_last_diff_ratio_nmos[05,00/0400]: 0.700000
LE_last_diff_ratio_pmos[05,00/0400]: 0.700000
LE_last_gate_cap[05,00/0400]: 0.400000
LE_local_gate_cap[05,00/0400]: 0.400000
LE_last_def_wire_ratio[05,00/0400]: 0.166600
LE_local_global_fanout_effort[05,00/0400]: 4.500000
LE_local_diff_ratio_nmos[05,00/0400]: 0.700000
LE_local_diff_ratio_pmos[05,00/0400]: 0.700000
LE_local_def_wire_ratio[05,00/0400]: 0.166600
LE_local_max_iterations[01,00/0400]: 40
LE_local_keeper_size_adj[05,00/0400]: 0.100000
LE_last_max_iterations[01,00/0400]: 40
LE_last_keeper_size_adj[05,00/0400]: 0.100000
LE_last_top_level_facet[04,00/0400]: "top{sch}"
LE_local_convergence_epsilon[05,00/0400]: 0.100000
LE_local_fanout_attr[04,00/0400]: "su"
LE_diffn_attr[04,00/0400]: "diffn"
LE_diffp_attr[04,00/0400]: "diffp"
LE_wire_length_attr[04,00/0400]: "L"
LE_last_sized_fanout[05,00/0400]: 0.000000
LE_export_le_attr[04,00/0400]: "le"
aidname: network
aidname: drc
aidname: erc
aidname: simulation
aidname: project
userbits: 3
techcount: 16
techname: generic lambda: 2000
techname: nmos lambda: 4000
techname: cmos lambda: 4000
techname: mocmos lambda: 400
techname: mocmosold lambda: 2000
techname: mocmossub lambda: 400
techname: bicmos lambda: 2000
techname: rcmos lambda: 2000
techname: cmosdodn lambda: 2000
techname: bipolar lambda: 4000
techname: schematic lambda: 4000
techname: fpga lambda: 2000
techname: pcb lambda: 2540000
techname: artwork lambda: 4000
techname: gem lambda: 2000
techname: efido lambda: 20000
view: schematic-page-2{p2}
view: schematic-page-1{p1}
view: layout{lay}
view: schematic{sch}
view: icon{ic}
view: documentation{doc}
view: compensated{comp}
view: skeleton{sk}
view: Verilog{ver}
view: VHDL{vhdl}
view: netlist{net}
view: netlist-als-format{net-als}
view: netlist-quisc-format{net-quisc}
view: netlist-silos-format{net-silos}
view: netlist-rsim-format{net-rsim}
view: netlist-netlisp-format{net-netlisp}
view: simulation-snapshot{sim}
view: unknown{}
cellcount: 1
maincell: 0
variables: 1
USER_electrical_units[01,00/0400]: 70464
***cell: 0
name: LogicalEffortLoad{ic}
version: 1
creationdate: 1014853513
revisiondate: 1014863037
lowx: -4000 highx: 4000 lowy: -13000 highy: 0
aadirty: 13278
userbits: 131074
nodes: 7 arcs: 0 porttypes: 1
variables: 2
prototype_center[02201,00/0400]: [0,0]
ATTR_Capacitance[0105,020200004040/010000000300]: 0.000000
**node: 0
type: artwork:Opened-Polygon
lowx: 0 highx: 0 lowy: -4000 highy: 0
rotation: 0 transpose: 0
userbits: 3072
variables: 2
trace[04201,00/0400]: [0,2000,0,-2000]
ART_color[01,00/0400]: 26
**node: 1
type: artwork:Opened-Polygon
lowx: -4000 highx: 4000 lowy: -6000 highy: -6000
rotation: 0 transpose: 0
userbits: 3072
variables: 2
trace[04201,00/0400]: [-4000,0,4000,0]
ART_color[01,00/0400]: 26
**node: 2
type: artwork:Opened-Polygon
lowx: -4000 highx: 4000 lowy: -4000 highy: -4000
rotation: 0 transpose: 0
userbits: 3072
variables: 2
trace[04201,00/0400]: [-4000,0,4000,0]
ART_color[01,00/0400]: 26
**node: 3
type: artwork:Opened-Polygon
lowx: 0 highx: 0 lowy: -10000 highy: -6000
rotation: 0 transpose: 0
userbits: 3072
variables: 2
trace[04201,00/0400]: [0,2000,0,-2000]
ART_color[01,00/0400]: 26
**node: 4
type: generic:Facet-Center
lowx: 0 highx: 0 lowy: 0 highy: 0
rotation: 0 transpose: 0
userbits: 8424448
**node: 5
type: schematic:Bus_Pin
lowx: 0 highx: 0 lowy: 0 highy: 0
rotation: 0 transpose: 0
userbits: 3072
*port: bus
exported: 0
**node: 6
type: artwork:Closed-Polygon
lowx: -3000 highx: 3000 lowy: -13000 highy: -10000
rotation: 0 transpose: 0
userbits: 3072
variables: 2
trace[06201,00/0400]: [-3000,1500,3000,1500,0,-1500]
ART_color[01,00/0400]: 26
**porttype: 0
subnode: 5
subport: bus
name: tap
descript: 0/512
userbits: 92160
celldone: LogicalEffortLoad
